from the Technology Interface

The following is a VHDL listing and simulation of a positive edge triggered d-type flip-flop. This is your first building block to learn when constructing sequential machines.

library ieee;
use ieee.std_logic_1164.all;
                          --  Positive Edged Triggered D-type FF
entity dflip is port (
 	d,clk: in std_logic;   -- defines the inputs
 	q:  out std_logic );   -- defines the output
end dflip;

architecture example of dflip is
    begin
	process(clk) begin
  	if (clk'event and clk = '1') then  -- make the transition responsive to the positive edge of clock
   	q <=d;    -- q is assigned the valuen of d
  	end if;
    end process;
end example;






The simulation shows that the output "q" is assigned
the value of the input "d" on the positive edge of clock
as defined by the if (clk'event and clk = '1')
statement.