VHDL Routines

the Technology Interface / Winter98

VHDL Sample Routine A 4-bit Multiplexer from the Technology Interface

This is the VHDL code for a 4-bit multiplexer. The select lines s0 and s1 chose either input "a,b,c, or d" to appear on the output "a".



library ieee;
use ieee.std_logic_1164.all;
entity mux is port (
         a,b,c,d:  in std_logic;
         s:        in std_logic_vector(1 downto 0);
         x:        out std_logic);
end mux;

architecture archmux of mux is
begin
with s select
       x < =    a when "00",
               b when "01",
               c when "10",
               d when others;
end archmux;

The simulation of the 4-to-one multiplexer. Notice that the output "x" follows the selected input (a,b,c,d) determined by select lines s0 and s1.